Polarization doping in nitride based diodes

ABSTRACT

A light emitting device comprising a three-dimensional polarization-graded (3DPG) structure that improves lateral current spreading within the device without introducing additional dopant impurities in the epitaxial structures. The 3DPG structure can include a repeatable stack unit that may be repeated several times within the 3DPG. The stack unit includes a compositionally graded layer and a silicon (Si) delta-doped layer. The graded layer is compositionally graded over a distance from a first material to a second material, introducing a polarization-induced bulk charge into the structure. The Si delta-doped layer compensates for back-depletion of the electron gas at the interface of the graded layers and adjacent layers. The 3DPG facilitates lateral current spreading so that current is injected into the entire active region, increasing the number of radiative recombination events in the active region and improving the external quantum efficiency and the wall-plug efficiency of the device.

This application is a divisional of, and claims the benefit of, U.S.patent application Ser. No. 11/900,952, filed on Sep. 14, 2007.

This invention was made with Government support under Contract No. USAF05-2-5507. The Government has certain rights in this invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to materials used in polar andsemi-polar semiconductor devices and, more particularly, topolarization-induced bulk doping techniques to reduce the seriesresistance of light emitting diodes (LEDs) and improve lateral currentspreading.

2. Description of the Related Art

Light emitting diodes (LED or LEDs) are solid state devices that convertelectric energy to light, and generally comprise one or more activelayers of semiconductor material sandwiched between oppositely dopedlayers. A bias is applied across the doped layers, injecting holes andelectrons into the active layer where they recombine to generate light.Light is emitted from the active layer and from all surfaces of the LED.A typical high efficiency LED comprises an LED chip mounted to an LEDpackage, wire-bonded to make electrical contacts, and encapsulated by atransparent medium. The efficient extraction of light is a major concernin the fabrication of LEDs.

A useful measure of the efficiency of an LED is the wall-plugefficiency. This is a measure of the electrical-to-optical powerconversion. Much effort has been devoted to improving the wall-plugefficiency of LEDs. One way to do this is to decrease the seriesresistance of the LED which in turn lowers the operating voltage. Eachinternal component or layer of the LED contributes to the total seriesresistance. Thus, reducing the resistance of any component or layerwould also reduce the total series resistance of the LED. Lowering theresistance of the p- and the n-cladding layers of an LED improveslateral current spreading, especially when the lateral current spreadingis entirely due to a semiconductor layer rather than a high conductivitymetal contact layer.

A known method for reducing resistance is by bulk doping an electronicmaterial with impurities. With impurity doping the carrier concentrationand transport properties are determined by temperature, dopantconcentration and scattering mechanisms such as impurity doping andphonon scattering. The carrier mobility is always diminished by theionized impurity scattering. The carrier concentration is reduced astemperature decreases. These problems led to research in the area ofmodulation doping which has been shown to improve low temperaturecarrier mobility in quantum-confined structures by many orders ofmagnitude.

Recently, group III-nitrides (e.g, AlN, BN, GaN, InN) have emerged asimportant materials for high-power microwave electronic and LEDapplications. Crystals such as group-III nitrides, when grown along the[0001] or the [000-1] direction of the wurtzite structure, exhibit largeembedded electronic polarization fields owing to the lack of inversionsymmetry in the crystal structure. This suggests the existence of adipole in each unit cell of the crystal. For a homogeneous bulk crystalsurface, dipoles inside the crystal cancel and leave net oppositecharges on the opposing crystal surface, which is characterized byspontaneous polarization. Dipoles can also be created when a crystal isunder strain, characterized by piezoelectric polarization. Bothspontaneous polarization and piezoelectric polarization have beenexploited for applications in communications, radar, infrared imaging,tunnel junction diodes, high-electron mobility transistors, memories,integrated optics, and in many other fields.

In one of the most popular nitride electronic devices, high-electronmobility transistors (HEMTs), the strong spontaneous and piezoelectricpolarization fields in AlGaN and GaN have been used to make nominallyundoped two-dimensional electron gases (2DEGs) in AlGaN/GaNheterostructures. [See Mishra et al., United States Patent ApplicationPublication No. US 2006/0231860 A1 (Oct. 19, 2006)]. These devices canyield excellent power and efficiency performance at microwavefrequencies.

Research in polarization doping in HEMT devices recently led to thedevelopment of three dimensional electron slabs that are usable as bulkdoped carriers. This is done by grading the heterojunction of a materialsystem such as AlGaN/GaN over a distance to spread the positivepolarization charge into a bulk three-dimensional polarizationbackground charge. The removal of ionized impurity scattering results inhigher mobilities and better operation at lower temperatures.Experimental results have shown more than an order of magnitudeimprovement of carrier mobility at low temperatures for the polarizationdoped system over comparable donor-doped system. [See Jena et al.,Realization of wide electron slabs by polarization bulk doping in gradedIII-V nitride semiconductor alloys, Applied Physics Letters, Vol. B1,No. 23 (December 2002)].

SUMMARY OF THE INVENTION

An embodiment of a light emitting device comprises an n-typesemiconductor layer, a p-type semiconductor layer, and an active regioninterposed between the n-type layer and the p-type layer. Athree-dimensional polarization-graded (3DPG) structure is disposed onthe n-type layer the active region.

An embodiment of a three-dimensional polarization-graded (3DPG) lateralcurrent spreading device, grown along the [0001] direction of a wurtzitecrystal structure, comprises a retrograded layer that is compositionallygraded from a first material to a second material over a gradingdistance and a silicon (Si) delta-doped layer disposed adjacent to theretrograded layer, such that the first material is proximate to the Sidelta-doped layer.

An embodiment of a three-dimensional polarization-graded (3DPG) lateralcurrent spreading device, grown along the [000-1] direction of awurtzite crystal structure, comprises a graded layer that iscompositionally graded from a second material to a first material over agrading distance and a silicon (Si) delta-doped layer disposed adjacentto the graded layer, such that the first material is proximate to the Sidelta-doped layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 a is a cross-sectional view of a light emitting device accordingto an embodiment of the present invention, grown along the [0001]direction or on Ga-face.

FIG. 1 b is a graph of a computer simulation that corresponds to thedevice of FIG. 1 a.

FIG. 1 c is a graph of another computer simulation that corresponds tothe device of FIG. 1 a.

FIG. 2 a is a cross-sectional view of a light emitting device accordingto an embodiment of the present invention, grown along the [0001]direction or on Ga-face.

FIG. 2 b is a graph of a computer simulation that corresponds to thedevice of FIG. 2 a.

FIG. 3 a is a cross-sectional view of a light emitting device, grownalong the [0001] direction or on Ga-face, according to an embodiment ofthe present invention.

FIG. 3 b is a graph of a computer simulation that corresponds to thedevice of FIG. 3 a.

FIG. 4 a is a cross-sectional view of a light emitting device, grownalong the [0001] direction or on Ga-face, according to an embodiment ofthe present invention.

FIG. 4 b is a graph of a computer simulation that corresponds to thedevice of FIG. 4 a.

FIG. 5 a is a cross-sectional view of a light emitting device, grownalong the [0001] direction or on Ga-face, according to an embodiment ofthe present invention.

FIG. 5 b is a graph of a computer simulation that corresponds to thedevice of FIG. 5 a.

FIG. 6 a is a cross-sectional view of a light emitting device accordingto an embodiment of the present invention, grown along the [000-1]direction or on N-face.

FIG. 6 b is a graph of a computer simulation that corresponds to thedevice of FIG. 6 a.

FIG. 6 c is a graph of another computer simulation that corresponds tothe device of FIG. 6 a.

FIG. 7 a is a cross-sectional view of a light emitting device accordingto an embodiment of the present invention, grown along the [000-1]direction or on N-face.

FIG. 7 b is a graph of a computer simulation that corresponds to thedevice of FIG. 7 a.

FIG. 8 a is a cross-sectional view of a light emitting device, grownalong the [000-1] direction or on N-face, according to an embodiment ofthe present invention.

FIG. 8 b is a graph of a computer simulation that corresponds to thedevice of FIG. 8 a.

FIG. 9 a is a cross-sectional view of a light emitting device, grownalong the [000-1] direction or on N-face, according to an embodiment ofthe present invention.

FIG. 9 b is a graph of a computer simulation that corresponds to thedevice of FIG. 9 a.

FIG. 10 a is a cross-sectional view of a light emitting device, grownalong the [000-1] direction or on N-face, according to an embodiment ofthe present invention.

FIG. 10 b is a graph of a computer simulation that corresponds to thedevice of FIG. 10 a.

DETAILED DESCRIPTION OF THE INVENTION

The present invention as embodied in the claims provides improvedmaterials and material configurations for use in semiconductor devices.Although the novel structures and methods presented are useful in manydifferent semiconductor applications, they are particularly well-suitedfor use in polar or semi-polar nitride-based LED systems to reduce theseries resistance and the operating voltage of these devices.

The series resistance R_(s) of an LED can be modeled by the equation:

R _(s) ≡R _(c)(n)+R _(c)(p)+R _(b)(n)+R _(b)(p)

where R_(c)(n) and R_(c)(p) represent the contact resistances for n- andp-contacts, respectively, and R_(b)(n) and R_(b)(p) represent the bulkresistance of the n- and p-type epitaxial layers, respectively. Forexample, a nominal 460 nm GaN LED has a bandgap of 2.7 eV. Assuming alossless system, the LED would also have an operating voltage of 2.7 eV.However, in reality there are voltage penalties associated with eachcomponent contributing to the series resistance. This voltage penaltycan be described as an “excess voltage” above the nominal bandgapvoltage. Thus, by reducing the series resistance of the individualcomponents, the excess voltage can be reduced, resulting in asignificant improvement in the wall-plug efficiency of the device andlateral current spreading in the LEDs.

The largest contribution to the overall excess voltage required by anitride-based LED comes from the bulk resistivity of the n-type layers.The excess voltage required by these layers also increases with higheroperating currents of the LED. This makes the improvement potential evengreater as solid state lighting devices trend toward operation at highercurrents in order to reduce cost. Higher bulk n-resistance also preventslateral current spreading, resulting in current crowding near theelectrical contacts and resulting non-uniform illumination of the LEDs.

Traditionally, semiconductor materials in LEDs have been doped byintroducing impurities into the crystal lattice of the varioussemiconductor layers. As a result of the impurities in the lattice, themobility of carriers is reduced by impurity scattering as the carriersmove through the lattice. Donor-doped materials also suffer from reducedcarrier mobility as temperature decreases. The thermally activatedcarriers “freeze out” with lowering temperatures which results in lessenergetic carriers and less effective screening. And this in turn leadsto significant ionized impurity scattering. Further, heavy doping oftenresults in cracking, deterioration of the surface morphology, etc.Growing thicker layers is another way of reducing the bulk resistivity,but in most circumstances, thicker layers result in wafer bowing,cracking, etc., due to the strains associated with heteroepitaxy.

Embodiments of the present invention reduce the resistance of one ormore of the epitaxial layers by engineering the band structure of polarnitride devices to induce excess free carriers in the bulk. Instead ofadditional impurity doping to increase the charge, the layers featurepolarization-induced bulk doping. The discontinuity in the polarizationacross a heterojunction, for example, InGaN/GaN, forms a fixedpolarization sheet charge at the heterojunction. By grading theheterojunction over a distance the sheet charge can be spread into abulk three-dimensional (3D) polarization background charge.

The fixed background charge attracts free carriers from remotedonor-like states to satisfy Poisson's equation and neutralize charge.The polarization bulk charge acts as a local donor with zero activationenergy. Thus, a mobile 3D electron slab is formed and can be used justlike bulk doped carriers without the associated impurity scattering andperformance degradation at low temperatures. The carriers exhibit highmobilities, and the resistance of the epitaxial layers is reduced.

Lower resistance in the epitaxial layers allows electrons to move moreeasily through the crystal lattice, vertically and laterally, on theirway to the active region. Good lateral movement in the lattice isimportant as it allows the current to spread out across the entire widthof the device before the carriers reach the active region. Thus, theentire area of the active region is available for recombination andemission.

It is understood that when an element such as a layer, region orsubstrate is referred to as being “on” another element, it can bedirectly on the other element or intervening elements may also bepresent. Furthermore, relative terms such as “inner”, “outer”, “upper”,“above”, “lower”, “beneath”, and “below”, and similar terms, may be usedherein to describe a relationship of one layer or another region. It isunderstood that these terms are intended to encompass differentorientations of the device in addition to the orientation depicted inthe figures.

Although the terms first, second, etc. may be used herein to describevarious elements, components, regions, layers and/or sections, theseelements, components, regions, layers and/or sections should not belimited by these terms. These terms are only used to distinguish oneelement, component, region, layer or section from another region, layeror section. Thus, a first element, component, region, layer or sectiondiscussed below could be termed a second element, component, region,layer or section without departing from the teachings of the presentinvention.

It is noted that the terms “layer” and “layers” are used interchangeablythroughout the application. A person of ordinary skill in the art willunderstand that a single “layer” of semiconductor material may actuallycomprise several individual layers of material. Likewise, several“layers” of material may be considered functionally as a single layer.In other words the term “layer” does not denote an homogenous layer ofsemiconductor material. A single “layer” may contain various dopantconcentrations and alloy compositions that are localized in sub-layers.Such sub-layers may function as buffer layers, contact layers oretch-stop layers, for example. These sub-layers may be formed in asingle formation step or in multiple steps. Unless specifically statedotherwise, the Applicant does not intend to limit the scope of theinvention as embodied in the claims by describing an element ascomprising a “layer” or “layers” of material.

Embodiments of the invention are described herein with reference tocross-sectional view illustrations that are schematic illustrations ofidealized embodiments of the invention. As such, variations from theshapes of the illustrations as a result, for example, of manufacturingtechniques and/or tolerances are expected. Embodiments of the inventionshould not be construed as limited to the particular shapes of theregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. A region illustrated ordescribed as square or rectangular will typically have rounded or curvedfeatures due to normal manufacturing tolerances. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the precise shape of a region of a device andare not intended to limit the scope of the invention.

FIG. 1 a illustrates an epitaxial device 100, grown along the [0001]crystal direction, according to an embodiment of the present invention.A bias can be applied across the layers with contacts (not shown) onboth ends of the structure, for example. In response to the bias, chargecarriers are transported through a p-type layer 102 and an n-type layer104 to the active region 106 where radiative recombination takes place,causing light within a specific wavelength range to be emitted from thedevice 100. The device 100 can be included in many different LEDpackages that include elements such as reflectors, secondary optics,wavelength conversion materials, and many others.

The device 100 includes a three-dimensional polarization-gradedstructure (3DPG) 108 which is disposed adjacent to the n-type layer 104opposite the active region 106 as shown. In this particular embodimentthe 3DPG comprises two polarization-graded layers 110 with a silicon(Si) delta-doped layer 112 interposed between them. The graded layers110 can comprise various materials including Al_(x)Ga_(1-x)N,In_(x)Ga_(1-x)N, Al_(x)In_(1-x)N and Al_(x)Ga_(y)In_(1-x-y) (where,x+y=1), or any material like Al_(x)B_(y)Ga_(z)In_((1-x-y-z))N (where,x+y+z=1), for use in a (Al, B, Ga, In)N system. For purposes ofconvenience only the InGaN/GaN system and Si-delta-doped layer, grownalong [0001] and [000-1] direction, will be referred to throughout theapplication as an exemplary system. It is understood that other materialsystems (for example AlGaN/GaN, AlInN/GaN, etc.), other delta-dopedelements (for example Mg, Be, Zn, etc.), other crystal growth directions(for example [10-1-1], [10-11], [10-1-3], [10-13], [11-2-2], etc.) andother nitride systems are also possible.

Here, the graded layers 110 are retrograded from InGaN to GaN (forgrowth along [0001] direction or Ga-face) over a distance that is equalto the width of the graded layer 110 in the growth direction. Becausethe layers 110 are retrograded, InGaN having the highest concentrationof In is disposed farthest from the junction with the n-type layer 104.In the figures a higher concentration of In is indicated by the darkershaded regions. The arrow in FIG. 1 a indicates the direction ofdecreasing In concentration. In a preferred embodiment, the gradedlayers 110 are retrograded from In_(0.1)Ga_(0.9)N to GaN over thegrading distance (i.e., the width of the layer in the growth direction)for each graded layer 110. Grading the heterojunction spreads thepositive polarization sheet charge into a bulk three-dimensionalpolarization background charge. As free electrons are induced in theretrograded layer, the polarization-induced electrons add to theexisting electrons obtained by doping, and together they reduce theoverall resistance of the structure 108. The 3DPG structure 108 allowsthe charge carriers be injected at various points on the bottom surface114 of the 3DPG. Because the carriers move easily in a lateraldirection, by the time the current reaches the active region 106, it isspread more evenly across the entire face of the active region 106.Using more of active region for recombination significantly improves theillumination uniformity, the wall-plug efficiency, and the overallperformance of a device.

The charge profile of the device is given by the divergence of thepolarization field, which changes only along the growth direction of thelayers. In a preferred embodiment a linear retrograde is used. A linearretrograde will yield an approximately uniform charge profile. However,it is possible to create non-uniform charge profiles using more exoticgradients, such as a parabolic gradient, for example.

As shown, it is possible to stack multiple graded layers 110 on tocreate a larger 3DPG structure. However, the negative sheet charge atthe interface between the high concentration InGaN of one graded layerand the GaN portion of the adjacent graded layer causes a back-depletionof the electron gas and a discontinuity of the electron profile at theinterface. This creates a hump-like barrier in the conduction band thatresults in electrical isolation. In order to compensate for theback-depletion a thin Si delta-doped layer 112 is interposed between thegraded layers 110. The Si delta-doped layer 112 reduces the conductionband barrier nearly to flat-band. Si delta-doped GaN layers are known inthe art and can be grown using known metalorganic chemical vapordeposition (MOCVD) processes. The Si delta-doped GaN layer compensatesfor the back-depletion, and provides free charges for continuity invertical conductivity, without deteriorating the surface morphology ofthe device.

FIG. 1 b and FIG. 1 c are graphs of computer simulations illustratingthe electron concentration profile along the height (i.e., in the growthdirection which is [0001] in this case) of the device 100, where nrepresents the number of electrons at a given distance. FIG. 1 b showsthe valence band (E_(v)) and conduction band (E_(c)) energies measuredin eV on the same graph for convenience. FIG. 1 c shows the electronprofile along the growth direction of the device 100 with the materialinterfaces delineated on the graph for reference. Three simulated datasets are shown on the graph: a device without retrograded layers; adevice with retrograded layers but without a Si delta-doped layer; and adevice with retrograded layers and with a Si delta-doped layer. Thefirst rise in electron concentration 140 occurs at the interface of thep-type layer 102 (e.g., p-GaN) and the n-type layer 104 (e.g., n-GaN)somewhere within the active region 106. The second rise in electronconcentration 142, which is a result of the polarization-induced bulkdoping in the graded layers 110, appears at the interface of the n-typelayer 104 and one of the graded layers 110.

After the second rise, a sharp positive spike in electron concentration144 is noticeable followed by a sharp negative spike 146. These sharpfeatures are due to the Si delta-doped layer 112 which is interposedbetween the two graded layers 110. The device having the retrogradedlayer but not having a Si delta-doped layer exhibits a large trough-likedrop 148 in electron concentration at the interface between the gradedlayers. This is due to the back-depletion of carriers as discussedabove. The low concentration of carriers over this distance introduces agreat resistance to current flowing across the interface, or verticallyalong the structure, and is undesirable. Juxtaposed with the trough 148,the negative spike 146 exhibited by the device featuring a Sidelta-doped region is much narrower (i.e., on the order of a singlenanometer) and provides a much less resistive current path. There is nodiscontinuity in electron flow or path. The device 100 that features theretrograded layers and the Si delta-doped region exhibits a superiorelectron concentration profile, allowing for current to flow easily tothe active region.

FIG. 2 a shows an epitaxial device 200 according to an embodiment of thepresent invention. The device 200, grown along the [0001] direction,functions similar to the device 100 and shares several common elements.In this particular embodiment the 3DPG structure 202 features anadditional graded layer and Si delta-doped layer pair. The graded layers110 in this embodiment are retrograded. Because total charge must beconserved, it is not possible to attain a high charge density over athick graded layer. In order to achieve a higher bulk charge severalgraded layers 110 can be stacked on top of each other. The graded layers110 are coupled together with Si delta-doped layers 112 in between tocompensate for the back-depletion of charge carriers at the respectiveinterfaces. The graded layer/delta-doped layer pair forms a repeatablestack unit 204. Additional stack units can be easily added to thestructure in order to add thickness while retaining a desired chargedensity. The resulting stacked structure has a higher free electronconcentration without the use of excessive external dopants which canraise the resistance of the device and cause cracking and otherirregularities in surface morphology.

FIG. 2 b is a graph of a computer simulation showing the electronconcentration profile (n=number of electrons) over a distance (nm) inthe growth direction of the device 200. The graph also shows the valenceband (E_(v)) and conduction band (E_(c)) energies measured in eV on thesame graph for convenience. Similarly as shown in FIG. 1 b, the firstand second rises in the electron concentration occur at the materialinterfaces on either side of the n-type layer 102. The thin spikeddiscontinuities 240 are due to the multiple Si delta-doped layers 112that are interposed between the graded layers 110. The small negativespikes indicating a sharp drop in electron concentration are narrowenough that they do not introduce any significant resistance to thecurrent path from the graded layers 110 to the active region 106.

FIG. 3 a illustrates an epitaxial device 300 according to an embodimentof the present invention. The device 300, grown along the [0001]direction, functions similar to the device 100 and shares many commonelements. In this particular embodiment, the 3DPG structure 302 featuresa uniformly doped spacer layer 304 interposed between a Si delta-dopedlayer 112 and a graded layer 110. The graded layer 110, the Sidelta-doped layer 112 and the spacer layer 304 form a repeatable stackunit 306. The stack unit may be repeated many times within the 3DPGstructure 302. Each stack unit that is included adds thickness andcharge to the device 300.

The spacer layer is doped uniformly with impurities at the sameconcentration as the graded layers 110. In the InGaN/GaN system, forexample, the spacer layer 304 can comprise a GaN layer. The spacer layer304 allows thicker devices to be grown. Thick layers can provide neededmechanical support to the device 300. Also, as thickness of the growthlayers increases, the defect density in the crystal structure isreduced. Because GaN layers can be grown much faster than InGaN layersand under much more moderate growth conditions, it is moretime-efficient to grow GaN layers to improve the morphology and addthickness to the devices.

FIG. 3 b shows a computer simulation of the electron concentrationprofile along the growth direction of the device 300. The profile issimilar to those in FIG. 1 b and FIG. 2 b. After the Si delta-dopedspike the electron concentration drops down to the level of the normallydoped n-type layer 104. This is because the spacer layer 304 does nothave polarization-induced doping. The level again rises at the interfaceof the spacer layer 304 and another graded layer 110.

FIG. 4 a depicts an epitaxial device 400 according to an embodiment ofthe present invention. The device 400, grown along the [0001] direction,is similar to device 300 and shares several common elements. In thisparticular embodiment, the 3DPG structure 402 comprises a series ofrepeatable stack units 404. Each stack unit 404 comprises a spacer layer406, a graded layer 408 and a Si delta-doped layer 410. The first stackunit 404 is disposed such that the spacer layer 406 is adjacent to then-type layer 407. A terminal layer 412 is adjacent to the Si delta-dopedlayer 410 in the stack unit 404 that is distal to the active region 106.In the InGaN/GaN system, the terminal layer 412 can comprise a InGaNlayer or a GaN layer, for example. A p-contact 414 is disposed on thep-type layer 102. An n-contact 416 is disposed on the terminal layer 412opposite the p-contact 414. Together the contacts 414, 416 provide aconnection to a bias source (not shown).

A preferred embodiment of the device 400 is now described. FIG. 4 a onlyshows two full stack units 404; however, the dashed lines along thesides of the device are meant to indicate that additional stack unitsmay be repeated up to the interface with the n-type layer 407. Apreferred embodiment of the device 400 comprises a stack unit 404 thatis repeated 15-20 times within the 3DPG structure 402. Each stack unit404 comprises: a linearly retrograded layer 408(n-In_(0.1)Ga_(0.9)N→n-GaN), approx. 25 nm thick; a Si delta-doped layer410, approx. 1 nm thick; and an n-GaN spacer layer 406, approx. 100 nmthick with 3e18 cm⁻³ donor doping. In the preferred embodiment, theterminal layer 412 comprises an approx. 50 nm thick n-GaN layer with3e18 cm⁻³ donor doping, and the n-type layer 407 comprises a 1 μm thickn-GaN layer with 3e18 cm⁻³ doping.

FIG. 4 b shows the results of a computer simulation of the device 400using the parameters of the preferred embodiment described above. Thegraph shows the electron concentration (n) along the growth direction(nm). The graph also shows the valence band (E_(v)) and conduction band(E_(c)) energies measured in eV on the same graph for convenience. Thefirst rise in electron concentration 440 on the left-hand side of thegraph is due to the interface at the n-type layer 407 which is dopedwith donor impurities to yield an n-type layer. The three tower-likestructures 430 on the right side of the graph represent the increase inelectron concentration due to three consecutive stack units 404.Although only two stack units 404 are shown in FIG. 4 a, it isunderstood that additional stack units 404 may be added.

Each of the three structures 430 includes an initial rise 442 thatcorresponds with the graded layer 408, a spike feature 444 thatcorresponds with the Si delta-doped layer 410, and a leveled-off region446 that corresponds with the spacer layer 406. The graph has beencondensed for viewing convenience. Although three tower-like structures430 appear in FIG. 4 b, it is understood that, in the preferredembodiment, 15-20 of the tower-like structures would appear on the graphcorresponding with each stack unit 404 within the 3DPG structure 402.

FIG. 5 a illustrates an epitaxial structure 500 according to anembodiment of the present invention. The device 500, grown along the[0001] direction, is similar to the devices 300, 400 in some aspects andshares several common elements. The 3DPG structure 504 may containseveral stack units 506. Each stack unit 506 comprises a spacer layer304, a graded layer 110, and a Si delta-doped layer 112. In oneembodiment there may be 15-20 stack units 506 within the 3DPG structure504. A terminal layer 412 is disposed adjacent to the stack unit 506farthest from the active region 106.

This particular embodiment features a top-side re-contact 502. Thetop-side n-contact 502 may be used to simplify the manufacturing processwhen devices are grown using a flip-chip process, for example. Flip-chipprocesses are known in the art. In this embodiment, the n-contact 502contacts one of the graded layers 110 within the 3DPG structure 504. Itis also possible to contact any of the other layers within the 3DPGstructure 504 with the n-contact 502. The device may be etched down tothe appropriate layer as shown in FIG. 5 a. Alternatively, a hole may beformed from the top surface with a via providing a connection to then-contact below, or the n-contact may be contacted from the side of thedevice. Other methods of connection may also be used.

Current enters the device at n-contact 502 and spreads laterally throughthe layers in the 3DPG structure 504. Thus, current may initially travelaway from the active region 106 to spread laterally before travelingvertically toward the active region 106. The 3DPG structure 504 provideseffective channels for the current to move laterally so that the currentis spread across the entire area of the active region 106, increasingthe radiative recombination and improving the illumination uniformity.

FIG. 5 b shows a graph of a computer simulation of device 500. Like theprevious graphs, the graph shows the electron concentration (n) alongthe growth direction (nm). The graph also shows the valence band (E_(v))and conduction band (E_(c)) energies measured in eV on the same graphfor convenience. The graph features three tower-like features 540 thatcorrespond to three stack units 506 within the 3DPG structure 504 and aninitial rise 542 at the p-n interface. It is understood that more orfewer stack units can be included within the 3DPG structure 504according to design needs. The tower-like features 540 are close to theinitial rise in electron concentration at the n-type layer 104. A thickterminal layer 412 is disposed adjacent to the stack unit 506 which isfarthest from the active region 106. The terminal layer 412 can beuniformly doped and can provide mechanical support to the device 500 aswell as improve the overall conductivity of the n-layer.

FIG. 6 a shows an epitaxial semiconductor device 600 according to anembodiment of the present invention. The device 600 is similar to device100 in some aspects and shares several common elements. However, unlikethe device 100, the device 600 is grown along the [000-1] crystaldirection. In the GaN material system, for example, the [000-1]direction represents the N-face of the crystal. The device features a3DPG 602 that is disposed adjacent to the n-type layer 104. In thisembodiment, the 3DPG 602 comprises a graded layer 604, a uniformly dopedn-type layer 606, and a Si delta-doped layer 608.

The graded layer 604 can comprise various materials includingAl_(x)Ga_(1-x)N, In_(x)Ga_(1-x)N, Al_(x)In_(1-x)N andAl_(x)Ga_(y)In_(1-x-y)N (where, x+y=1), or any material likeAl_(x)B_(y)Ga_(z)In_((1-x-y-z))N (where, x+y+z=1), for use in a (Al, B,Ga, In)N system. Here, using the GaN/InGaN system, for example, thegraded layer 604 is compositionally graded from GaN to InGaN over agrading distance (as indicated by the arrow in FIG. 6 a) along the[000-1] crystal direction. In one embodiment, the graded layer islinearly graded from GaN to In_(0.1)Ga_(0.9)N over the grading distance.Other compositions may also be used. The layer can be gradednon-linearly as well. As discussed above, a Si delta-doped layer 608 isinterposed between the graded layer 604 and the n-type layer 104 tocompensate for the back-depletion of the electron gas at this interface.The Si delta-doped layer 608 is disposed on the InGaN side of the gradedlayer 604, and because the graded layer 604 is graded, rather thanretrograded as in FIG. 1 a, the Si delta-doped layer 608 is adjacent tothe n-type layer 104.

FIG. 6 b is a graph of a computer simulation of device 600. The graphshows a first rise 640 in electron concentration at the p-n junction.The Si delta-doped layer 608 yields a sharp spike 642 in electronsfollowed by an increased level 644 of electrons in the graded layer 604.FIG. 6 c is another graph of a computer simulation of the device 600.The graph includes data sets for: a device without a graded layer or Sidelta-doped layer; a device with a graded layer but without a Sidelta-doped layer; and a device with both a graded layer and a Sidelta-doped layer. Vertical dashed lines demarcate the various layerswithin the device for ease of reference.

FIG. 7 a a cross-section of a semiconductor device 700 according to oneembodiment of the present invention. The device 700 is similar to thedevice 200 and shares several common elements. The device 700 comprisesa 3DPG 702. In this embodiment, the graded layer 604 (graded along the[000-1] crystal direction) and Si delta-doped layer 608 form arepeatable stack unit 704. Although only two stack units are shown, itis understood that more or fewer stack units can be incorporated in the3DPG 702. The device also includes a uniformly doped n-type terminallayer 606. FIG. 7 b is a graph of a computer simulation of the device700 similar to those discussed above which shows the expected electronlevels in the device. The graph shows two periods of simulation, each ofwhich corresponds to one of the stack units 704 shown in FIG. 7 a.

FIG. 8 a illustrates the cross-section of a semiconductor device 800according to an embodiment of the present invention. The device 800 issimilar to the device 300 and shares several common elements. The devicefeatures a 3DPG 802. In this embodiment, the 3DPG comprises multiplestack units each of which includes a Si delta-doped layer 608, a gradedlayer 604 (graded along the [000-1] crystal direction), and a uniformlydoped n-type spacer layer 806. Although only two stack units are shown,it is understood that more or fewer stack units can be incorporated intothe 3DPG 802. FIG. 8 b is a computer simulation of the device 800. Thegraph shows two periods of simulation, each of which corresponds to oneof the stack units 804 shown in FIG. 8 a.

FIG. 9 a shows the cross-section of a semiconductor device 900. Thedevice 900 is similar to the device 400 and shares several commonelements. The device 900 includes a 3DPG 902. In this embodiment, the3DPG 902 comprises multiple stack units 904 each of which includes a Sidelta-doped layer 608, a graded layer 604, and a uniformly doped n-typespacer layer 806. Although only two stack units 904 are shown, it isunderstood that stack unit 904 can be repeated many times within the3DPG 902. In a preferred embodiment the stack unit 904 is repeated 15-20times within the 3DPG 902. The device 900 also comprises p- andn-contacts 906, 908 disposed on the ends of the device 900 such that thep-contact 906 provides a connection to the p-type layer 102 and there-contact 908 provides a connection to the n-type side of the device900. The contacts 906, 908 are connected to an external voltage device(not shown) to bias the device during operation. FIG. 9 b is a graph ofa computer simulation of the device 900. The graph shows two periods ofsimulation, each of which corresponds to one of the stack units 904shown in FIG. 9 a. A full graph of the preferred embodiment would showbetween 15 and 20 similar periods, one for each stack unit included inthe device.

FIG. 10 a illustrates a cross-section of a semiconductor device 1000according to an embodiment of the present invention. The device 1000 issimilar to device 500 and shares several common elements. The device1000 comprises a 3DPG 1002 which has several repeatable stack units1004, each of which includes a Si delta-doped layer 608, a graded layer604 (graded along the [000-1] crystal direction), and a uniformly dopedn-type spacer layer 806. Although only two stack units 1004 are shown, apreferred embodiment has 15-20 stack units within the 3DPG 1002. Thedevice 1000 was formed by a flip-chip process with both the p-contact1006 and the n-contact 1008 disposed on the top side of the device 1000as shown. Flip-chip processes are known in the art.

In this embodiment, the n-contact 1008 contacts one of the graded layers604 within the 3DPG structure 1002 from the top side. Thus, the currentmoves laterally through the device 1000. It is also possible to contactany of the other layers within the 3DPG structure 1002 with then-contact 1008. The device may be etched down to the appropriate layeras shown in FIG. 10 a. Alternatively, a hole may be formed from the topsurface with a via providing a connection to the re-contact below, orthe 3DPG layers may be contacted from the side of the device. Othermethods of connection may also be used. A thick uniformly doped n-typelayer 1010 is disposed on the end of the device 1000 opposite the p-typelayer 102. The thick layer 1010 can provide mechanical support for thedevice 1000.

FIG. 10 b is a graph of a computer simulation of the device 1000. Onlytwo periods are shown which correspond to the two stack units 1004 inFIG. 10 a. It is understood that additional periods would be shown foreach additional stack unit included in the 3DPG 1002.

Although the present invention has been described in detail withreference to certain preferred configurations thereof, other versionsare possible. Therefore, the spirit and scope of the invention shouldnot be limited to the versions described above.

I claim:
 1. A light emitting device comprising: a plurality ofsemiconductor layers; an active region interposed between two of saidsemiconductor layers; and a three-dimensional polarization-graded (3DPG)structure disposed on a first of said semiconductor layers and oppositesaid active region; wherein said 3DPG structure comprises a graded layercompositionally graded from a first material to a second material over agrading distance.
 2. The light emitting device of claim 1, wherein said3DPG structure comprises at least one repeatable stack unit and aterminal layer disposed such that said at least one stack unit isinterposed between said first semiconductor layer and said terminallayer.
 3. The light emitting device of claim 2, said repeatable stackunit comprising: a graded layer that is compositionally graded from afirst material to a second material over a grading distance, said gradedlayer disposed proximate to said first semiconductor layer such thatsaid first material is closest to said first semiconductor layer; and adelta-doped layer interposed between said graded layer and said firstsemiconductor layer.
 4. The light emitting device of claim 3, whereinsaid graded layer has a linear compositional grading.
 5. The lightemitting device of claim 3, wherein said graded layer has a nonlinearcompositional grading.
 6. The light emitting device of claim 3, saidrepeatable stack unit further comprising an n-type spacer layer disposedadjacent to said graded layer opposite said delta-doped layer.
 7. Thelight emitting device of claim 6, wherein said n-type spacer layer isuniformly doped.
 8. The light emitting device of claim 3, wherein saidfirst material comprises indium gallium nitride of a first composition(In_(x)Ga_(1-x)N) and said second material comprises indium galliumnitride of a second composition (In_(y)Ga_(1-y)N), where x is greaterthan y and both x and y range between 0 and 1, inclusive.
 9. The lightemitting device of claim 8, wherein x is about 0.1 and y is about
 0. 10.The light emitting device of claim 3, wherein said repeatable stack unitis repeated 15 or more times within said 3DPG structure.
 11. The lightemitting device of claim 3, wherein said graded layer is approximately25 nm thick.
 12. The light emitting device of claim 3, wherein saiddelta-doped layer is approximately 1 nm thick.
 13. The light emittingdevice of claim 3, wherein said delta-doped layer is delta-doped withsilicon (Si).
 14. The light emitting device of claim 1, wherein saidfirst of said semiconductor layers is an n-type layer.
 15. The lightemitting device of claim 1, wherein said 3DPG structure has a wurtzitecrystal structure and is grown along the [000-1] crystal direction. 16.A current spreading device, comprising: a graded layer compositionallygraded from a first material to a second material over a gradingdistance; and a delta-doped layer disposed adjacent to said gradedlayer, such that said first material is proximate to said delta-dopedlayer.
 17. The current spreading device of claim 16, wherein said gradedlayer has a bulk three-dimensional polarization-induced backgroundcharge.
 18. The current spreading device of claim 16, wherein arepeatable stack unit comprises said graded layer and said delta-dopedlayer.
 19. The current spreading device of claim 16, further comprisingan n-type spacer layer disposed adjacent to said graded layer oppositesaid delta-doped layer such that said graded layer is interposed betweensaid delta-doped layer and said spacer layer.
 20. The current spreadingdevice of claim 19, wherein said graded layer and said spacer layer bothcomprise n-type semiconductor materials.
 21. The current spreadingdevice of claim 19, wherein a repeatable stack unit comprises saidgraded layer, said delta-doped layer, and said spacer layer.
 22. Thecurrent spreading device of claim 21, wherein said repeatable stack unitis repeated 15-20 times within said current spreading device.
 23. Thecurrent spreading device of claim 16, wherein said first materialcomprises indium gallium nitride of a first composition(In_(x)Ga_(1-x)N) and said second material comprises indium galliumnitride of a second composition (In_(y)Ga_(1-y)N), where x is greaterthan y and both x and y range between 0 and 1, inclusive.
 24. Thecurrent spreading device of claim 23, wherein x is about 0.1 and y isabout
 0. 25. The current spreading device of claim 16, wherein saidgraded layer is approximately 25 nm thick.
 26. The current spreadingdevice of claim 16, wherein said delta-doped layer is approximately 1 nmthick.
 27. The current spreading device of claim 16, wherein saiddelta-doped layer is delta-doped with silicon (Si).